1. Field
This disclosure relates generally to semiconductors, and more specifically, to the control of a data strobe signal used by synchronous interface control and storage circuitry.
2. Related Art
Synchronous dynamic random access memory (SDRAM) utilize one or more reference clock signals provided by a memory controller to manage data transfers via one or more data strobe signals in a data processing system. The input and output data of the SDRAM are synchronized in a predetermined relationship to a data strobe signal. Double data rate (DDR) SDRAMs allow data transfers at twice the clock rate in relationship to both the rising and falling edges of the data strobe.
Conventional DDR SDRAMs use a bi-directional data strobe signal commonly referred to as a DQS signal. A data strobe receiver receives the DQS signal from either SDRAM or a memory controller and functions to provide a reference strobe signal to properly capture data. DQS and data generated by the memory controller to SDRAM (write transfer) are required to meet setup and hold time requirements centered about DQS transitions while DQS and data generated by the SDRAM to the memory controller (read transfer) are valid between DQS transitions.
For example, DDR SRAM memory controllers and SDRAM use the DQS strobe signals to send data to the SDRAM (write transfers) and receive data from the SDRAM (read transfers). The DQS data strobe signal functions as a reference timing signal to enable data capture. It is a requirement of industry standards that data be centered about DQS transitions meeting setup and hold time requirements of the SDRAM for write transfers performed by an SDRAM controller and valid between DQS transitions from the SDRAM for read transfers performed by an SDRAM controller. Industry standards define several states of DQS before, during and after a transfer of data. Before a transfer of data, DQS is in a high-impedance state that is known as Hi-Z. When DQS is in Hi-Z, DQS is at an undefined voltage level between logic high and logic low. In the clock cycle immediately before a data transfer, DQS transitions from the Hi-Z high-impedance state to a logic low. This logic low state is known as a data strobe preamble. After the data strobe preamble, DQS transitions are used to synchronize the data transaction. One half clock before the data transfer is complete, while DQS is in a logic low state, is known as the data strobe postamble. After completion of the postamble, the DQS data strobe signal again enters the Hi-Z high-impedance state provided another transfer does not immediately begin. Because the DQS strobe signal is not driven until the data strobe preamble starts and is again stopped from being driven at the end of a transaction in the postamble, it is important that a data strobe receiver be turned on and off at precisely the correct time in order to generate an internal digital DQS strobe signal with the correct timing. Otherwise indeterminate control signal values may be generated or the internal DQS strobe signal may oscillate and thereby result in erroneous latching of information.